How to Choose the Right PCB Stackup

Start the discussion before dense routing is complete. A later change in material or dielectric spacing can require trace-width changes and a new impedance assessment. The objective is to agree a construction that supports the design, rather than forcing the manufacturing process to reproduce an undocumented CAD default.

Establish the electrical and mechanical constraints

List the interfaces that drive the design. A slow status signal, a fast digital interface, and a sensitive analog input do not necessarily need the same routing treatment. Edge behavior, frequency content, signal levels, and the surrounding circuit matter; clock frequency alone is not a sufficient way to classify every interconnect.

Then identify mechanical constraints: finished thickness at a connector, mounting locations, bending requirements, and component-height limits. Distinguish mandatory dimensions from preferences. If an enclosure fixes the board thickness while impedance requirements favor a different dielectric arrangement, that conflict should be resolved before the layout is considered released.

Assign useful reference layers

A signal is part of a circuit that includes a return path. For high-frequency components of current, the relationship between the routed conductor and its reference structure is important. A continuous nearby reference can make the return path more predictable; a slot or split can force a detour and increase the effective loop area.

Review the actual reference beneath a route, not only the layer name in the CAD tool. A layer labeled ground can still contain openings, isolated regions, or interruptions. A change between signal layers also changes the reference relationship and may require a deliberate return-current transition.

Adding copper layers does not automatically solve these issues. A poorly assigned six-layer construction can be less useful than a carefully planned four-layer construction for a particular circuit. The stackup and routing strategy have to work together.

Coordinate dielectric geometry with impedance requirements

Impedance depends on the conductor geometry and its surrounding materials and conductors. Trace width, copper thickness, distance to reference, dielectric properties, and neighboring features can all be relevant. A differential pair also introduces the relationship between the two traces.

Ask for a proposed manufacturable stackup and agree which values are fixed before calculating the final routing geometry. Do not use a generic online calculator to prescribe a width while leaving the material and dielectric thickness undefined. A calculator or field solver is useful only when its inputs represent the intended construction.

If impedance verification is required, document the target, tolerance, associated layers, and relevant structures. Agree the measurement method and any coupon requirements. An impedance note without identifying the applicable signals or layers creates an avoidable interpretation problem.

Choose materials by their relevant properties

FR-4 is not one identical material. Specific laminate systems have their own electrical, thermal, mechanical, and processing characteristics. Compare data at appropriate test conditions, including frequency and method where they affect interpretation. A nominal dielectric constant from an unrelated construction is not automatically the correct design input.

Thermal requirements also need more than a headline Tg value. Decomposition behavior, expansion, moisture, and the anticipated assembly and operating exposure may matter. Material selection should consider the product and manufacturing process together. See the FR-4 material guide for a more detailed selection framework.

Use a stackup decision table

Worked example: selecting between four and six layers

Suppose an instrument board contains a processor, a sensitive analog front end, and several connectors. A four-layer proposal provides two outer routing layers and two inner planes. During placement review, dense connector escapes and the analog routing compete for the available outer-layer space. The engineer should first assess whether placement and partitioning can solve the conflict without damaging the reference continuity.

A six-layer alternative can provide additional routing choices while retaining useful reference layers. It is not automatically the winner: compare how the signals actually reference the planes, the via transitions needed, the achievable construction, and the cost and schedule implications. The decision is justified by the routing and verification needs, not by an assumption that six is inherently high quality and four is inherently inadequate.

Neither example establishes a universal layer assignment. Record the selected construction and the reasons for it so a later revision does not accidentally replace an important reference layer with unrestricted routing.

Keep the approved stackup connected to the released files

Once the construction is agreed, use consistent layer names in the CAD exports and drawing. Identify the revision of the approved stackup and any changes requiring review. A material substitution that appears commercially convenient may change electrical design assumptions, so it should not be hidden inside purchasing correspondence.

For a multilayer PCB quotation, submit the fabrication files and proposed stackup together. If the layout is still developing, the PCB design and layout service can coordinate the manufacturing and mechanical constraints before release.

Common mistakes to avoid

• Finalizing dense routing before confirming the intended construction.
• Treating a plane label as proof of an uninterrupted reference path.
• Copying impedance geometry without matching its material and spacing inputs.
• Changing copper or dielectric requirements without rechecking the whole stack.
• Treating one published material property as complete qualification for the product.